High-performance bipolar transistors are vertical bipolar transistors, as opposed to lateral bipolar transistors. A vertical bipolar transistor, for example an npn bipolar transistor 2 schematically shown in FIG. 1, comprises an n+ type emitter region 3, a p type base region 4, and an n type collector region 5 stacked one on top of the other. In order to reduce collector series resistance, there is usually an n+ type subcollector layer 6 beneath the collector region 5 and an n+ type reachthrough region 7 is used to bring the collector contact to the surface.
In normal operation, the emitter-base diode is forward biased, and the base-collector diode is reverse biased. The entire n type collector layer is usually thick enough to accommodate the space-charge region (also called the depletion region since it is normally depleted of mobile carriers) and a quasi-neutral region. The thickness, or width, of the space-charge region is determined by the collector doping concentration and the base-collector bias voltage. The quasi-neutral collector region can be very thin, usually just thick enough to prevent the space-charge region from reaching the n+ type subcollector layer. If the base-collector space-charge region touches the n+ type subcollector, it will cause the base-collector junction capacitance to increase and the base-collector junction breakdown voltage to decrease. The n+ type subcollector layer is usually rather thick, typically thicker than 1000 nm, in order to achieve an adequately small collector series resistance.
In normal operation, electrons are injected from the emitter E and collected at the collector C. The dotted arrow shown in FIG. 2 indicates the electron path in normal operation, starting from the emitter contact. FIG. 3 is the energy-band diagram along the electron path. In FIGS. 2 and 3, A indicates the location of the emitter contact, A′ indicates the boundary between the depleted part and the quasi-neutral part of the n type collector, and A″ indicates the top of the n+ subcollector layer. In FIG. 3, the ordinate represents electron and hole energy.
A more detailed description of the basic structure and operation of a bipolar transistor can be found in the book by Yuan Taur and Tak H. Ning entitled Fundamentals of Modern VLSI Devices, Chapter 6, Bipolar Devices, Cambridge University Press, 1998, pp 292-347 which is incorporated herein by reference.
Vertical bipolar transistors have been built in the silicon layer of SOI. FIG. 4 illustrates a vertical npn bipolar transistor 2′ using SOI. Usually, it is simply a vertical bipolar transistor, including its n+ type subcollector layer 6, sitting on a buried oxide layer 9 and substrate 8 of the SOI. The SOI silicon layer has to be rather thick, thick enough to accommodate the various layers of a vertical bipolar transistor described above.
SOI BiCMOS obtained from the integration of a vertical bipolar transistor with CMOS devices using SOI has been described in a publication by Toshiro Hiramoto, et al., “A 27 GHz double polysilicon bipolar technology on bonded SOI with embedded 58 μm2 CMOS memory cells for ECL-CMOS SRAM applications,” IEDM Technical Digest, pp. 39-42, 1992.
The thick silicon layer needed for the bipolar transistor results in the CMOS devices behaving like regular bulk CMOS devices, rather than like high-speed SOI CMOS devices. The silicon layer of high-speed SOI CMOS is usually rather thin, typically less than 200 nm, much too thin to accommodate present vertical bipolar transistor structures.
It is possible to significantly reduce the silicon thickness needed for making SOI vertical bipolar transistors 2″ by omitting the relatively thick n+ subcollector layer 6. This structure is illustrated in FIG. 5. The electrons still flows the same way as in a vertical bipolar transistor with a subcollector layer, namely vertically through the base layer and through the depletion layer of the base-collector diode to the quasi-neutral collector region. However, without the n+ subcollector layer 6, electron current will have to be carried by the quasi-neutral collector layer which has very high sheet resistance because of its relatively light doping concentration and relatively small thickness compared to the n+ type subcollector layer 6. The resulting collector series resistance is unacceptably large. If the n type collector thickness is increased significantly to reduce collector series resistance, the resultant SOI silicon layer will again be much to thick for integration with high-speed SOI CMOS devices.